Integrated circuit (IC) structures have middle of the line (MOL) contacts that connect the semiconductor devices to back end of the line (BEOL) metal levels. For example, a field effect transistor (FET) can have a gate contact (also referred to herein as a CB contact) and source/drain contacts (also referred to herein as CA contacts). The gate contact can extend vertically through interlayer dielectric (ILD) material from a metal wire or via in the first back end of the line (BEOL) metal level (referred to herein as M0) to the gate of the FET. The source/drain contacts can extend vertically through ILD material from metal wires or vias in the BEOL metal level to metal plugs (also referred to herein as TS contacts), which are on the source/drain regions of the FET. Historically, in order to avoid shorts between the gate contact and the metal plugs, the gate contact is formed on a portion of the gate that is offset from the active region of the FET and, more particularly, on a portion of the gate that extends laterally over the adjacent isolation region. However, given the ever present need for size scaling of devices, it would be advantageous to provide a method that, not only allows for a gate contact to be formed on a portion of the gate directly above the active region (referred to herein as a CB-over-active or CBoA) or close thereto, but ensures that the risk of a short developing between the gate contact and any of the metal plugs is avoided (or at least significantly reduced).